業績リスト

Journals

[1] CH Lee, YC Tsai, HC Chang, JH Liu, HW Hu, H. Ito, YS Kim, T. Ohba, and KN Chen, “Electrical Characteristics and Reliability of Wafer-on-Wafer (WOW) Bumpless Through Silicon Via,” IEEE Transactions on Electron Devices to be published in 2021.
[2] S. Sugatani, N. Chujo, K. Sakui, H. Ryoson, T. Nakamura, and T. Ohba, “Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) Technology with 3D-manner Redundancy Scheme,” Jpn. J. of Applied Phys. to be published in 2021.
[3] S. Sugatani, N. Chujo, K. Sakui, H. Ryoson, T. Nakamura, and T. Ohba, “Vertically Replaceable Memory Block Architecture for Stacked DRAM Systems by Wafer-on-Wafer (WOW) Technology,” IEEE Transactions on Electron Devices, Vol. 67 (11), pp. 4606-4610, 2020.
[4] Yi-Lun Yang, H. Ito, Y. S. Kim, T. Ohba, and KN Chen, “Evaluation of Metal/Polymer Adhesion and Highly Reliable Four-Point Bending Test Using Stealth Dicing Method in 3-D Integration,” IEEE Transactions on Components, Packaging and Manufacturing Technol., Vol.10 (6), pp. 956-962, 2020, DOI: 10.1109/TCPMT.2020.2968561.
[5] Y. Okamoto, H. Ryoson, K. Fujimoto, T. Ohba, and Y. Mita, “On-Chip CMOS-MEMS-Based Electroosmotic Flow Micropump Integrated with High-Voltage Generator,” J. Microelectromechanical Systems, Vol. 29 (1), pp. 86-94, 2020 (2020.02) doi: 10.1109/JMEMS.2019.2953290
[6] S. Lee, J.-H Kim, Y. S. Kim, T. Ohba, T.-S Kim, "Effects of Thickness and Crystallographic Orientation on Tensile Properties of Thinned Silicon Wafers," IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 10 (2), pp. 296-303, 2020.
[7] Y. Okamoto, H. Takehara, K. Fujimoto, T. Ichiki, T. Ohba, and Y. Mita, " On-Chip High-Voltage Charge Pump with MEMS Post-Processed Standard 5-V CMOS on SOI for Electroosmotic Flow Micropumps,” IEEE Electron Device Letters, 39, pp. 851-854 (2018). (doi: 10.1109/LED.2018.2829925)
[8] T. Ohba, Y. S. Kim, Y. Mizushima, N. Maeda, K. Fujimoto, and S. Kodama, “Review of Wafer-Level Three-Dimensional Integration (3DI) using Bumpless Interconnects for Tera-Scale Generation,” IEICE Electronics Express, vol. 12 (7), pp. 1-14, DOI: 10.1587/elex.12.20150002 (2015).
[9] Y. Mizushima, Y. S. Kim, T. Nakamura, R. Sugie, H. Hashimoto, A. Uedono, and T. Ohba, “Impact of back-grinding-induced damage on Si wafer thinning for three-dimensional integration,” Jpn. J. Appl. Phys., vol. 53, 05GE04, 2014.
[10] N. Taoka, O. Nakatsuka, Y. Mizushima, H. Kitada, Y. S. Kim, T. Nakamura, T. Ohba, and S. Zaima, “Observation of lattice spacing fluctuation and strain undulation around through-Si vias in wafer-on-wafer structures using X-ray microbeam diffraction,” Jpn. J. Appl. Phys. 53, 05GE03 (2014).
[11] A. Uedono, Y. Mizushima, Y. S. Kim, T. Nakamura, T. Ohba, N. Yoshihara, N. Oshima, and R. Suzuki, “Vacancy-type defects induced by grinding of Si wafers studied by mono-energetic positron beams,” J. Appl. Phys 116, 134501 (2014)
[12] Y. Mizushima, H. Kitada, C. J. Uchibori, N. Maeda, S. Kodama, Y. S. Kim, K. Fujimoto, S. Yoshimi, T. Nakamura, and T. Ohba, “Impact of Thermomechanical Stresses on Bumpless Chip in Stacked Wafer Structure, Jpn. J. Appl. Phys. 52 (2013) 05FE01
[13] Y. S. Kim, N. Maeda, H. Kitada, K. Fujimoto, S. Kodama, A. Kawai, K. Arai, K. Suzuki, T. Nakamura, T. Ohba, “Advanced wafer thinning technology and feasibility test for 3D integration,” Microelectronic Engineering, Volume 107, July 2013, Pages 65–71
[14] Y. S. Kim, “3D Integration using Bumpless Wafer-on-Wafer (WOW) Technology,” Journal of the Microelectronics & Packaging Society, 19(4), pp.71-78, 2012.
[15] Y. Mizushima, H. Kitada, C. J. Uchibori1, N. Maeda, S. Kodama, Y. S. Kim, K. Fujimoto, S. Yoshimi, and T. Nakamura, T. Ohba, “Impacts of Thermo-Mechanical Stresses on Bumpless Chip in Stacked Wafer Structure,” Jpn. J. Appl. Phys., to be published.
[16] Y. S. Kim, N. Maeda, H. Kitada, K. Fujimoto, S. Kodama, A. Kawai, K. Arai, K. Suzuki, T. Nakamura, and T. Ohba, “Advanced Wafer Thinning Technology and Feasibility Test for 3D Integration,” Proc. Mat. for Advanced Metallization (MAM), O104 (2012); Microelectronic Eng., Elsevier, to be published in 2012.
[17] T. Ohba, “Bumpless Through-Dielectrics- Silicon- Via (TDSV) Technology for Wafer- based Three-Dimensional Integration (3DI),” Electrochem. Soc. Trans. 44 (1), 827-840 (2012).
[18] Y. Mizushima, H. Kitada, K. Koshikawa, S. Suzuki, T.Nakamura, T. Ohba, “Novel TSV Leakage Current Evaluation using IR- Optical Beam Irradiation,” Jpn. J. Appl. Phys., 51 (2012) DOI: 10.1143/ JJAP.51.05EE03.
[19] T. Ohba, “Three-Dimensional (3D) Integration Technology,” Electrochem. Soc., Trans., 34 (1), pp. 1011-1016 (2011).
[20] D. Diehl, H. Kitada, N. Maeda, K. Fujimoto, S. Ramaswami, K. Sirajuddin, R. Yalamanchili, B. Eaton, N. Rajagopalan, R. Ding, S. Patel, Z Cao, R. Kulzer, I. Drucker, D. Erickson, T. Ritzdorf, T. Nakamura, and T. Ohba, “Formation of TSV for the Stacking of Advanced Logic Devices Utilizing Bumpless Wafe r-on-Wafer Technology,” Microelectron. Eng., 92, pp. 3-8 (2011).
[21] O. Nakatsuka, H. Kitada, Y. S. Kim, Y. Mizushima, T. Nakamura, T. Ohba, and S. Zaima, “Characterization of Local Strain around Through-Silicon-Via Interconnects by Using X-ray Microdiffraction,” Jpn. J. Appl. Phys., 50 (5), 05ED03 (2011).
[22] H. Kitada, N. Maeda, K. Fujimoto, Y. Mizushima, Y. Nakata, T. Nakamura, and T. Ohba, “Diffusion Resistance of Low Temperature Chemical Vapor Deposition Dielectrics for Multiple Through Silicon Via on Bumpless Wafer-on-Wafer Technology,” Jpn. J. Appl. Phys., 50 (5), 05ED02 (2011).
[23] H. Machida, S. Hamada, T. Horiike, M. Ishikawa, A. Ogura, Y. Ohshita, and T. Ohba, “Chemical Vapor Deposition of GeSbTe Thin Films for Next-Generation Phase Change Memory,” Jpn. J. Appl. Phys. 49 (2010) 05FF06.
[24] S. Tominaga, D. Abe, T. Enomoto, S. Kondo, H. Kitada, and T. Ohba, “Hybrid Electrochemical Mechanical Planarization Process for Cu Dual-Damascene Through-Silicon Via Using Noncontact Electrode Pad,” Jpn. J. Appl. Phys., 49 (2010) 05FG01.
[25] T. Ohba, N. Maeda, H. Kitada, K. Fujimoto, K. Suzuki, T. Nakamura, A. Kawai, and K. Arai, “Thinned Wafer Multi-stack 3DI Technology,” Microelectronic Eng., Elsevier, 87 pp. 485-490 (2010).
[26] Y. Kitaoka, T. Tono, S. Yoshimoto, T. Hirahara, S. Hasegawa, and T. Ohba, “Direct detection of grain boundary scattering in damascene Cu wires by nanoscale four-point probe resistance measurements,” Appl. Phys. Lett., 95 (2009); DOI: 10.1063/1.3202418
[27] H. Kim, T. Koseki, T. Ohba, T. Ohta, Y. Kojima, H. Sato, S. Hosaka and Y. Shimogaki, “Effect of Ru crystal orientation on the adhesion characteristics of Cu for ultra-large scale integration interconnects,” Applied Surface Science, 252 (11), 31, pp. 3938-3942, 2006.
[28] H. Kim, Y. Naito, T. Koseki, T. Ohba, T. Ohta, Y. Kojima, H. Sato and Y Shimogaki, “Material Consideration on Ta, Mo, Ru, and Os as Glue Layer for Ultra Large Scale Integration Cu Interconnects,” Jpn. J. Appl, Phys., 45 (4A), pp. 2497-2501, 2006.
[29] H. Kim, T. Koseki, T. Ohba, T. Ohta, Y. Kojima, H. Sato and Y. Shimogaki, “Cu wettability and diffusion barrier property of Ru thin film for Cu metallization,” J. Electrochem. Soc. 152 (8), G594, 2005.
[30] H. Kim, T. Koseki, T. Ohba, T. Ohta, Y. Kojima, H. Sato and Y. Shimogaki, “Process design of Cu(Sn) alloy deposition for highly reliable ultra large-scale integration interconnects,” Thin Solid Films 491 (1-2), pp. 221-227, 2005.
[31] T. Ohba, “A Study of Current Multilevel Interconnect Technologies for 90 nm Nodes and Beyond,” FUJITSU Sci. Tech. J., 38 (1), pp.13-21, 2002.
[32] T. Ohba, “Material and Process Challenges in 100-nm Interconnects Module Technology and Beyond,” J. Electronic Materials, 30 (4), pp. 314-319, 2001.
[33] T. Ohba, “Chemical-Vapor-Deposited Tungsten for Vertical Wiring,” MRS Bulletin, 20 (11), pp. 46-52, 1995): DOI: https://doi.org/10.1557/S0883769400045565
[34] T. Ohba, “Advanced Multilevel Metallization Technology,” Appl. Surface Sci., 91 (1-4), pp. 1-11, 1995: https://doi.org/10.1016/0169-4332(95)00086-0
[35] N. Misawa, T. Ohba, and H. Yagi, “Planarized Copper Multilevel Interconnections for ULSI Applications,” MRS Bulletin, 19 (8), pp. 63-67, 1994: DOI: https://doi.org/10.1557/S088376940004776X
[36] T. Ohba T. and Y. Furumura, “Chemical Vapor Deposition of Tungsten by Reduction of WF6, SiH4, Si2H6, Si3H8, B2H6, PH3, and H2,” J. of the Institution of Electronics and Telecommunication Engineers, 37 (2), pp. 212-219, 1991.
[37] I. Narisawa and T. Ohba, “An Evaluation of Acoustic Emission from Fibre-Reinforced Composites,” J. Mater. Sci., 20 (12), pp. 4527-4531, 1985.

International Conferences

[1] Z. Chen, YS Kim, T. Fukuda, K. Sakui, T. Nakamura, T. Kobayashi, T. Obara, and T. Ohba, “Ultra-Thinning of 20 nm-Node DRAMs down to 3 mm for Wafer-on-Wafer (WOW) Applications,” IEEE ECTC to be presented in 2021.
[2] T. Funaki, Y. Satake, K. Kobinata, CC Hsiao, H. Matsuno, S. Abe, YS Kim, and T. Ohba, “Miniaturized 3D Functional Interposer using Bumpless Chip-on-Wafer (COW) Integration with Capacitors,” IEEE ECTC to be presented in 2021.
[3] T. Aoki, M. Hirasawa, K. Izunome, and T. Ohba, “Development of Novel Bevel Profile for Wafer-level Stacking Technology,” Int’l Conf. on Electronics Packaging (ICEP) Conf. to be presented in 2021.
[4] Y. Satake, K. Kobinata, T. Funaki, Y. S. Kim, and T. Ohba, “Voidless Chip-on-Wafer Process for Functional Interposer,” Int’l Conf. on Electronics Packaging (ICEP) Conf. to be presented in 2021.
[5] Z. Chen, YS Kim, T. Fukuda, K. Sakui, T. Kobayashi, T. Obara, and T. Ohba, “Reliability of Wafer-Level Ultra-Thinning down to 3 μm using 20 nm-Node DRAMs,” IEEE Int’l Reliability Phys. Symp. (IRPS) to be presented in 2021.
[6] T. Aoki, M. Hirasawa, K. Izunome, and T. Ohba, “Evaluation of Critical Bevel Angle for Ultra-Thinning of Wafer” Int’l Microsystems, Packaging, Assembly and Circuits Technology Conf. (IMPACT), 2020, pp. 79-81.
[7] Y. Okamoto, Y. Mita, H. Ryoson, and T. Ohba, “Cooling Measurement of On-Chip Inetgrated EOF Micropump Using CMOS-LSI Components,” 2020 Int’l Conf. on Solid State Devices and Materials (SSDM 2020), pp. 137-138, 2020.
[8] S. Sugatani, N. Chujo, K. Sakui, H. Ryoson, T. Nakamura, and T. Ohba, “Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) Technology with 3D-manner Redundancy Scheme,” 2020 Int’l Conf. on Solid State Devices and Materials (SSDM 2020), pp. 145-146, 2020.
[9] Y. Satake, T. Funaki, K. Tabata, K. Kobinata, and YS Kim, and T. Ohba, “Development of Functional Interposer Using Bumpless Chip-on-Wafer,” 2020 Int’l Conf. on Solid State Devices and Materials (SSDM 2020), pp. 119-120, 2020.
[10] Chujo, K. Sakui, H. Ryoson, S. Sugatani, T. Nakamura, and T. Ohba, “Bumpless Build Cube (BBCube): High-Parallelism, High-Heat-Dissipation and Low-Power Stacked Memory Using Wafer-Level 3D Integration Process,” IEEE VLSI Symp., TH1.3, 2020.
[11] Suzuki, T. Nakamura, Y. Kondo, S. Tominaga, K. Atsumi, and T. Ohba, “Damage-Less Singulation of Ultra-Thin Wafers using Stealth Dicing,” 2020 IEEE 70th Electronic Components and Technology Conf. (ECTC), pp. 1043-1049, 2020.
[12] Araki, S. Maetani, Y. S. Kim, T. Hirota, T. Nakamura, and T. Ohba, “Material Optimization of Permanent and Temporary Adhesives for Wafer-level Three-dimensional Integration,” 2020 IEEE 70th Electronic Components and Technology Conf. (ECTC), pp. 55-61, 2020.
[13] Ohba, "Wafer Level 3D Application for Tera-byte Node," 21st Int’l Conf. on Electronic Materials and Packaging (ISMP-EMAP 2019), p. 43, 2019.
[14] Ho Ahn, S. Lee, Y. S. Kim, T. Ohba, and T. -S. Kim, "Effect of Femtosecond Laser Machining Environment on Mechanical Behaviors of Thinned Silicon," 21st Int’l Conf. on Electronic Materials and Packaging (ISMP-EMAP 2019), p. 121, 2019.
[15] Nakamura, and T. Ohba, "Stress-distribution analysis of micron-thick DRAM wafer for WOW application," Proc. 16th Int’l Conf. on Reliability and Stress-related Phenomena in Nano and Microelectronics (IRSP), (2019)
[16] a-Hsuan Lee, Hsin-Chi Chang, Jui-Han Liu, H. Ito, Y. S. Kim, Kuan-Neng Chen, and T. Ohba, “Temperature Cycling Reliability of Wow Bumpless Through Silicon Vias,” IEEE 3D System Integration Conf., Sendai, Japan, Oct 8 – Oct 10, 2019.
[17] Ohba,"3D Integration for High Bandwidth Application," 15th Int’l Microsystems, Packaging, Assembly and Circuits Technology Conf. (IMPACT-IAAC), 2019.
[18] Maetani, N. Araki, Y. S. Kim, S. Kodama, and T. Ohba, "Study of Thermal characteristics of thin adhesive layer using novel RDP method for Wafer-On-Wafer (WOW) Applications," 15th Int’l Microsystems, Packaging, Assembly and Circuits Technology Conf. (IMPACT-IAAC), 2019.
[19] Ohba, "Size-Reduction of HBW System using WOW Bumpless TSV Interconnects," 2019 Int'l Conf. on Solid State Devices and Materials, pp. 417-418, 2019.
[20] Ohba, “Interconnects for Tera-byte 3D Application," IEEE Int'l Interconnect Technol. Conf. and the Materials for Advanced Metallization Conf. (IITC/MAM), invited talk, 2019.
[21] Araki, 3, S. Maetani, Y. S. Kim, S. Kodama, and T. Ohba, "Development of Resins for Bumpless Interconnects and Wafer-On-Wafer (WOW) Integration," IEEE 69th Electronic Components and Technology Conf. (ECTC). pp.1002-1007, 2019.
[22] Sakui and T. Ohba, "High Speed, Low Power, and Ultra-small Operating Platform with Three-dimensional Integration (3DI) by Bumpless Interconnects," IEEE 11th Int'l Memory Workshop (IMW), pp. 60-63, 2019.
[23] Lun Yang, Jia-Ling Liu, Guan Wei Chen, S. Kodama, K. Kobinata, Kuan-Neng Chen, H. Ito, Y. S. Kim, and T. Ohba, “Highly Reliable Four-Point Bending Test Using Stealth Dicing Method for Adhesion Evaluation,” 2019 Int’l Conf. on Electronics Packaging (ICEP) Conf., Toki Messe, Niigata, Japan, Apr. 17-20, 2019.
[24] Maetani, N. Araki, Y. S. Kim, S. Kodama, and T. Ohba, "New Adhesive Design and Evaluation for Bumpless Interconnects and Wafer-On-Wafer (WOW) Integration," Int'l Conf. on Electronics Packaging (ICEP), pp. 411-413, Apr. 17-20, 2019.
[25] Sakui and T. Ohba, "Three-dimensional Integration (3DI) with Bumpless Interconnects for Tera-scale Generation ~ High Speed, Low Power, and Ultra-small Operating Platform (Invited)," IEEE Custom Integrated Circuits Conf. is a premier Conf. (CICC), 2019.
[26] Okamoto, K. Fujimoto, H. Ryoson, T. Ohba, and Y. Mita, "Stick-to-Analyze Zeta Potential Measurement Chip with Integrated Electroosmotic Micropump and Liquid Flow Sensor,” The 32th Int’l Conf. on Micro Electro Mechanical Systems (MEMS 2019), Seoul, Korea (2019.01).
[27] Fujimoto Y. Okawa, Y. Hiroi, J. Katayama, T. Funakoshi, Y. Yanagida and T. Ohba "QUANTITATIVE ANALYSIS OF CELL ADHESION UNDER SHEAR STRESS USING MICROFLUIDIC DEVICES,” 22th Int’l Conf. on Miniaturized Systems for Chemistry and Life Sciences, 2018, p.2472-2473, (2018).
[28] Suzuki, K. Atsumi, N. Uchiyama, and T. Ohba, “Improving Throughput of Zero-Kerf Singulation for Ultra-Thin Wafers using Stealth Dicing,” The 13th Int’l Microsystems, Packaging, Assembly and Circuit Technology Conf. (IMPACT), Taiwan, pp. 156–158 (2018).
[29] Araki, Y. S. Kim, S. Kodama, C. Hsiao, H. Chang, C. Lin, and T. Ohba, “Development of Micrometer-Thick Bonding Material for Wafer-On-Wafer (WOW) Applications,” IMPACT2018 Oct. 24-26, (2018)
[30] Suzuki, Y. Kondo, K. Atsumi, N. Uchiyma, and T. Ohba, "High Throughput and Improved Edge Straightness for Memory Applications using Stealth Dicing," IEEE 68th Electronic Components and Technology Conf. (ECTC). pp.2174-2179, 2018.
[31] S. Kim, S. Kodama, Y. Mizushima, N. Araki, C. Hsiao, H. Chang, C. Lin, and T. Ohba,“Optimization of Via Bottom Cleaning for Bumpless Interconnects and Wafer-On-Wafer (WOW) Integration,” Proceedings of the Electronic Components and Technology Conf. (ECTC), pp.1962, (2018)
[32] Lee, JH Kim, T. Ohba, Y. S. Kim, and T.S. Kim, “A Study on Mechanical Properties of Thinned Single Crystal Silicon wafer;Effects of Size and Tensile Direction,” Int’l Conf. on Electronics Packaging (ICEP), pp 339.,(2018)
[33] Nakamura, Y. Mizushima, Y. S. Kim, S. Kodama, and T. Ohba, “Novel in-plane inspection of micron-thick DRAM wafer using Raman imaging for WOW application,” Proc. Materilas for Advanced Metallization (MAM), (2018)
[34] Ohba, “Three Dimensional Stack Process for Tera-Byte DRAM Application using WOW Technology,” The 7th Int’l Conf. on Electronics, Communications and Networks (CENet), Nov. 24-27, 2017, National Dong Hwa University, Hualien, Taiwan
[35] Fujimoto Y. Okawa, Y. Hiroi, J. Katayama, T. Funakoshi, Y. Yanagida and T. Ohba "A SILICON BIOREACTOR WITH THREE-DIMENSIONAL FLOW-FOCUSING STRUCTURE TO GENERATE PLATELETS,” 21th Int’l Conf. on Miniaturized Systems for Chemistry and Life Sciences, 2017, p. 1491-1492, (2017)
[36] Mizushima, Y. S. Kim, S. Kodama, T. Nakamura, and T. Ohba, "Plan view stress distribution at 1 um underneath of DRAM device using WOW ultra-thinning technology," Proc. 27th Advanced Metallization Conf. (AMC) 2017 and ADMETA 2017.
[37] Ryoson, K. Fujimoto, and T. Ohba, " A Design Guide of Thermal Resistance down to 30% for 3D Multi-stack Devices,” ICEP2017, (2017)
[38] Ohba, "Ultra-Thinning Technologies for 300-mm Wafer Stack of 3D Semiconductor Application," Frontiers in Materials Processing Applications, Research and Technology (FiMPART), OP2251, 2017.
[39] Okamoto, H. Ryoson, K. Fujimoto, K. Honjo, T. Ohba, and Y. Mita, "Hotspot Liquid Microfluidic Cooling: Comparing the Efficiency between Horizontal Flow and Vertical Flow,” PowerMEMS, Paris, France, (2016.12)
[40] S. Kim, "Ultra Wafer Thinning less than 10-mm for 3D Multi-stack Wafer-On-Wafer (WOW) Application,” ENGE2016 (2016)
[41] Suzuki, Xiao Shiqin, K. Atsumi, N. Uchiyama, T. Ohba, “Laser Dicing for Higher Chip Productivity,” Proc. Int'l Microsystems, Packaging, Assembly and Circuit Technol. Conf. (IMPACT), Taiwan, pp. 242-244, 2016.
[42] S. Kim, "Ultra-Thinning of DRAM Wafers up to 2-um and Evaluation of Devices Characteristics for 3D Integration,” ISMP2016 (2016)
[43] Suzuki, Xiao Shiqin, K. Atsumi, N. Uchiyama, T. Ohba, “Laser Dicing for Higher Chip Productivity,” Proc. 26th Advanced Metallization Conf. (ADMETA), Japan, p. 66, 2016.
[44] Fujimoto, Y. Okawa, A. Tsukune, A. Aihara, Y. Hiroi, J. Katayama, T. Funakoshi, and T. Ohba, "A BIOREACTOR FOR PLATELET GENERATION WITH HIGH PRODUCTIVITY THROUGH NARROW SLITS OF PDMS,” 20th Int’l Conf. on Miniaturized Systems for Chemistry and Life Sciences, 2016, p. 1025-1026
[45] Ohba, "Three Dimensional Stack Process for Next-Gen LSI using WOW Technology,” IEEE CPMT Soc. Jpn. Chapter, Oct. 2016.
[46] Ohba, "Production-Worthy WOW 3DI Technology using Bumpless Interconnects and Ultra-Thinning Processes," IEEE VLSI Symp., pp. 184-185, 2016.
[47] S. Kim, S. Kodama, Y. Mizushima, T. Nakamura, N. Maeda, K. Fujimoto, A. Kawai, and T. Ohba,"Warpage-free Ultra-Thinning ranged from 2 to 5-μm for DRAM Wafers and Evaluation of Devices Characteristics,” ECTC2016., 1461 (2016)
[48] S. Kim, S. Kodama, N. Maeda, K. Fujimoto, Y. Mizushima, A. Kawai, TC Hsu, P.Tzeng, TK Ku, and T. Ohba, "Electrical Characteristics of Bumpless Interconnects for Through Silicon Via (TSV) and Wafer-On-Wafer (WOW) Integration,” ICEP2016., 74 (2016)
[49] Mizushima, Y. S. Kim, T. Nakamura, A. Uedono, and T. Ohba, "Behavior of Cu Contamination on Backside Damage for Ultra-thin Si 3D Stacking Structure," Proc. Materilas for Advanced Metallization (MAM) 2016.
[50] Ohba, "Ultra-Thinning of Silicon Device Wafer for 3D Semiconductor Application," BIT's 2nd Aworld Congress of Smart Materials, p. 64, 2016.
[51] S. Kim, S. Kodama, Y. Mizushima, T. Nakamura, N. Maeda, K. Fujimoto, A. Kawai, K. Arai, and T. Ohba, "A Robust Wafer Thinning down to 2.6-μm for Bumpless Interconnects and DRAM WOW Applications,” IEDM2015 Tech. Dig., 190 (2015)
[52] Fujimoto, Y. Okawa, A. Tsukune, A. Aihara, Y. Hiroi, J. Katayama, T. Funakoshi, and T. Ohba, "A NOVEL BIOREACTOR WITH HIGH PRODUCTIVITY FOR THE GENERATION OF PLATELETS USING MEMS TECHNOLOGIES,” 19th Int’l Conf. on Miniaturized Systems for Chemistry and Life Sciences, 2015, p. 1214-1216
[53] Ohba, "Bump-Free, Warpage-Free, and Ultra-Thin Wafer-on-Wafer Technology," IEEE Int'l Microsystems, Packaging, Assembly and Circuit Technol. Conf. (IMPACT), Session 21, Oct. 2015.
[54] Nakamura, Y. Mizushima, Y. S. Kim, R. Sugie, and T. Ohba, "Stress Distribution Analysis in Ultra-Thinned DRAM Wafer,”14th Int’l Symposium on Microelectronics and Packaging, Korea (2015).
[55] Mizushima, Y. S. Kim, T. Nakamura, R. Sugie, and T. Ohba, "Behavior of Copper Contamination for Ultra-Thinning of 300 mm Silicon Wafer down to <5 μm," Proc. Advanced Metallization Conf. (AMC) 2015 and ADMETA 2015.
[56] Ohba, "BEOL Friendly Bumpless Interconnects Technology for 3D-3D Integration," Proc. 25th Advanced Metallization Conf. (ADMETA), Korea, pp. 156-157, 2015.
[57] Nakamura, Y. Mizushima, Y. Suk Kim, R. Sugie, and T. Ohba, Stress Distribution Analysis in Ultra-Thinned DRAM Wafer, "Characterization of Stress Distribution in Ultra-Thinned DRAM Wafer,” 3DIC2015-62
[58] Nakamura, Y. Mizushima, Y. S. Kim, A. Uedono, and T. Ohba, “Impacts of Back Grind Damage on Si Wafer Thinning for 3D Integration,” ISMP 2014, 12nd Int’l Symposium on Microelectronics and Packaging
[59] Mizushima, Y. S. Kim, T. Nakamura, S. Kodama, N. Maeda, K. Fujimoto, T. Ohba, “Impact of Thermomechanical Stresses on Ultra-thin Si Stacked Structure,” IEEE Int’l 3D Sys. Integration Conf., Cork, 2014.
[60] Tanaka, K. Tsutsumi, Y. S. Kim, S. Kodama, Y. Mizushima, N. Maeda, K. Fujimoto, T. Nakamura, A. Kawai, K. Arai, and T. Ohba, “A Novel Adhesive Material Development for the Bumpless WOW 3D DRAM Applications,” Proc. Advanced Metallization Conf. (2014) and ADMETA 2014.
[61] S. Kim, S. Kodama, Y. Mizushima, N. Maeda, K. Fujimoto, T. Nakamura, A. Kawai, K. Arai, and T. Ohba, “Ultra Thinning of DRAM wafer for 3D WOW Application: Impact of Thinning on Retention Characteristic and Atomic Level Analysis of Backside Damage Layer,” Proc. Advanced Metallization Conf. (2014) and ADMETA 2014.
[62] amura, “Surface Characterization of Ultra-Thinned Silicon for 3D integration,” WORKSHOP on Surface Science and Semiconductors (WOTS 2014), Aug. 20, 2014.
[63] Ohba, “Post-Scaling and Three- Dimensional Integration in Semiconductors,” WORKSHOP on Surface Science and Semiconductors (WOTS 2014), Aug. 20, 2014.
[64] S. Kim, S. Kodama, Y. Mizushima, N. Maeda, H. Kitada, K. Fujimoto, T. Nakamura, D. Suzuki, A. Kawai, K. Arai, and T. Ohba, “Ultra Thinning down to 4-μm using 300-mm Wafer proven by 40-nm Node 2Gb DRAM for 3D Multi-stack WOW Applications,” IEEE Symp. on VLSI Technol., Honolulu, pp.26-27, 2014.
[65] Taoka, O. Nakatsuka, Y. Mizushima, H. Kitada, Y. S. Kim, T. Nakamura, T. Ohba, and S. Zaima, “Strain Distributions at Edge of Corner in Bonded Si in Chip-On-Wafer Structures,” Materials for Advanced Metallization, Chemnitz, 2014.
[66] -Chen Liao, Erh-Hao Chen, Chien-Chou Chen, Shang-Chun Chen, Jui-Chin Chen, Po-Chih Chang, Yiu-Hsiang Chang, Cha-Hsin Lin, Tzu-Kun Ku, Ming-Jer Kao, Young Suk Kim, N. Maeda, S. Kodama, H. Kitada, K. Fujimoto, T. Ohba, “An Innovative Bumpless Stacking with Through Silicon Via for 3D Wafer-On-Wafer (WOW) Integration,” IEEE Electronic Components and Technology Conf. (ECTC), Orlando, 2014, pp.1853-1856.
[67] Fukozu, K. Kashima, T. Ohba “Application for Rice Plant Cultivation using LSI Integration method 2. The effect of the growth environment of seedlings to the ion absorption.” Proc. The 60th JSAP spring Meeting, 30a-PB1-1, (2013)
[68] Nakamura, Y. Mizushima, H. Kitada, Y.S. Kim, N. Maeda, S. Kodama, R. Sugie, H. Hashimoto, A. Kawai, K. Arai, A. Uedono, and T. Ohba, “Influence of Wafer Thinning Process on Backside Damage in 3D Integration,” IEEE Int’l 3D Sys. Integration Conf. 2013
[69] Kitada, “Influence of Titanium Liner for Advanced Fine Pitch Cu-TSV's,” Proc. Int’l Workshop on Advanced Packaging & System Technology, Sept. 3, 2013.
[70] Mizushima, “Impact of Thermomechanical Stresses on Bumpless Chip in Stacked Wafer Structure,” Proc. Int’l Workshop on Advanced Packaging & System Technology, Sept. 3, 2013.
[71] Taoka, O. Nakatsuka, Y. Mizushima, H. Kitada, Y. S. Kim, T. Nakamura, T. Ohba and S. Zaima, “Strain Undulation around Through Si Vias in Wafer-On-Wafer Structures,” Proc. Int’l Workshop on Advanced Packaging & System Technology, Sept. 3, 2013.
[72] Fujimoto, “Development of cooling system with closed channel for three dimensional integration devices,” Proc. Int’l Workshop on Advanced Packaging & System Technology, Sept. 3, 2013.
[73] Maeda, “Development of Bumpless COW using <20 μm thick 1Gbit DDR3 SDRAM for Tera-Scale Application,” Proc. Int’l Workshop on Advanced Packaging & System Technology, Sept. 3, 2013.
[74] Ohba, “Tera-Scale Three-Dimensional Integration (3D) using Bumpless TSV Interconnects,” Proc. Int’l Workshop on Advanced Packaging & System Technology, Sept. 3, 2013.
[75] S. Kim, N. Maeda, H. Kitada, K. Fujimoto, S. Kodama, A. Kawai, K. Arai, and T. Ohba, “Advanced Wafer Thinning Technology and Feasibility Test for 3D Integration,” Proc. Int’l Workshop on Advanced Packaging & System Technology, 2013.
[76] Kudo, Y. Oguri, A. Tsukune, Y. S. Kim, H. Kitada, K. Fjimoto, I. Kinefuchi, Y. Matsumoto, and T. Ohba, “High Performance Closed-Channel Cooling System Using Multi-channel Electro-osmotic Flow pumps for 3D-ICs,” IEEE Int’l Electron Devices Meeting (IEDM), Washington DC, 2013, pp. 480-483.
[77] Maeda, H. Kitada, K. Fujimoto, Y. S. Kim, S. Kodama, S. Yoshimi, Y. Mizushima, K. Masu, and T. Ohba, “Development of Bumpless COW using <20 μm thick 1 Gbit DDR3 SDRAM for Tera-Scale Application,” Proc. Advanced Metallization Conf., Albany, 2013.
[78] Ohba, “Wafer level three-dimensional integration (3DI) using bumpless TSV interconnects for tera-scale generation,” IEEE Semiconductor Conf. Dresden-Grenoble (ISCDG), pp. 1-4, 2013, DOI: 10.1109/ISCDG.2013.6656328
[79] Mizushima, Y. S. Kim, T. Nakamura, R. Sugie, H. Hashimoto, A. Uedono, T. Ohba, “Impacts of back grind damage on Si wafer thinning for 3D integration,” Proc. Advanced Metallization Conf., Albany, 2013.
[80] Ohba, “Tera-Scale Three-Dimensional Integration (3DI) using Bumpless TSV Interconnects,” IEICE Technical Report, Aug. 1, 2013.
[81] Ohba, “Three-Dimensional Technology for Tera-Byte Devices using COW and WOW Bumpless Interconnects,” Mat. Res. Soc., Spring Meeting, 2013.
[82] Fujimoto, S. Yoshimi, N. Maeda, S. Kodama, Y. S. Kim, H. Kitada, Y. Mizushima, T. Nakamura, K. Suzuki, T. Ohba, “Novel 3-Dimensional Integration Technique of Chip-On-Wafer (COW) for MEMS Applications,” Proc. DTIP, Spain, 2013.
[83] Fujimoto, N. Maeda, H. Kitada, Y. S. Kim, S. Kodama, T. Nakamura, K. Suzuki, T. Ohba, “Development of Cost-effective Wafer Level Process for 3D- Integration with Bump-less TSV Interconnects,” IEEE Electronic Components and Technology Conf. (ECTC), San Diego, 2012, pp.537-540.
[84] Maeda, H. Kitada, K. Fujimoto, Y. S. Kim, S. Kodama, S. Yoshimi, M. Akazawa, Y. Mizushima, and T. Ohba, “Development of Ultra-Thin Chip-on-Wafer Process using Bumpless Interconnects for Three-Dimensional Memory/Logic Applications,” Proc. 1st Int’l Workshop on Advanced Packaging & System Technology, pp. 37-38 (2012).
[85] Kitada, N. Maeda, K. Fujimoto, S. Kodama, Y. Mizushima, T. Nakamura, and T. Ohba, “Surface microroughness-induced leakage current in through-silicon via interconnects,” Proc. 1st Int’l Workshop on Advanced Packaging & System Technology, pp. 27-28 (2012).
[86] S. Kim, N. Maeda, H. Kitada, A. Kawai, K. Arai, K. Fujimoto, K. Suzuki, T. Nakamura, and T. Ohba, “Evaluation of ultra thinned-wafer employed high performance CMS devices for Wafer-on-Wafer (WOW) 3D Integration,” Proc. 1st Int’l Workshop on Advanced Packaging & System Technology, pp. 17-18 (2012).
[87] Fujimoto, N. Maeda, H. Kitada, Y. S. Kim, A Kawai, K. Arai, T. Nakamura, K. Suzuki, and T. Ohba, Proc. 1st Int’l Workshop on Advanced Packaging & System Technology, “Development of Multi-Stack Process on Wafer-on-Wafer (WOW),” pp. 7-8 (2012).
[88] Ohba, “Bumpless Interconnects Technology for Wafer- based Three- Dimensional Integration (3DI), Proc. 1st Int’l Workshop on Advanced Packaging & System Technology, pp. 3-4 (2012).
[89] Ohba, “Bumpless interconnects technology for wafer-based three-dimensional integration (3DI),” The Int’l Conf. “Micro- and Nanoelectronics – 2012” (ICMNE-2012), L1-04 (2012).
[90] Ohba, “Bumpless Through- Dielectrics- Silicon-Via (TDSV) Technology for Wafer- based Three- Dimensional Integration (3DI)” Proc. China Semiconductor Technology Int’l Conf. (CSTIC), (2012)
[91] C. Liao, C. H. Lin, E. H. Chen, T. Ohba, Y. S. Kim, S. Kodama, K. Fujimoto, H. Kitada, N. Maeda, P. J. Tzeng, J. C. Chen, S. C. Chen, C. Y. Wu, C. C. Chen, Y. C. Hsin, C. H. Chen, C.C. Wang, T. C. Hsu, T. K. Ku, and M. J. Kao, “Study of the Wafer Bow Variation During Re-distribution Layer (RDL) and Probe Pad Formation for 3DIC Wafer-on-Wafer (WOW) Application,” Proc. Advanced Metallization Conf. (2012) and ADMETA 2012.
[92] Yoshimi, M. Akazawa, K. Fujimoto, K. Suzuki, N. Maeda, Y. S. Kim, H. Kitada, S. Kodama, Y. Mizushima, and T. Ohba, “Development of Dielectric Polymer Etching for Chip-on-Wafer Process using Bump-less Off-Chip-Via Interconnects,” Proc. Advanced Metallization Conf. (2012) and ADMETA 2012.
[93] Mizushima, H. Kitada, C. J. Uchibori1, N. Maeda, S. Kodama, Y. S. Kim, K. Fujimoto, S. Yoshimi, T. Nakamura, and T. Ohba, “Impacts of Thermo-Mechanical Stresses on Bumpless Chip in Stacked Wafer Structure,” Proc. Advanced Metallization Conf. (2012) and ADMETA 2012.
[94] Fujimoto, N. Maeda, H. Kitada, A.Kawai, K.Arai, T. Nakamura, K. Suzuki, T. Ohba, “Development of Product-worthy process for 3D-Integration with a stack of WOW(wafer-on-wafer),” IEEE ECTC2012, pp. 537-540 (2012)
[95] Maeda, H. Kitada, K. Fujimoto, Y. S. Kim, S. Kodama, S. Yoshimi, M. Akazawa, Y. Mizushima, and T. Ohba, “Development of Ultra-Thin Chip-on-Wafer Process using Bumpless Interconnects for Three- Dimensional Memory/ Logic Applications, IEEE VLSI Symp., 171 (2012).
[96] Maeda, Y. S. Kim, Y. Hikosaka, T. Eshita, H. Kitada, K. Fujimoto, Y. Mizushima, K. Suzuki, T. Nakamura, A. Kawai, K. Arai and T. Ohba, “Development of Ultra-thinning Technology for Logic and Memory Heterogeneous Stack Applications,” IEEE Int’l 3D Sys. Integration Conf. 2011, P-1-19 (2012).
[97] Nakatsuka, H. Kitada, Y. S. Kim, Y. Mizushima, T. Nakamura, T. Ohba and S. Zaima, “Characterization of Local Strain around Trough Silicon Via Interconnects in Wafer-on-wafer Structures,” IEEE Int’l 3D Sys. Integration Conf. 2011, 9-3 (2012).
[98] Nakamura, H. Kitada, Y. Mizushima, N. Maeda, K. Fujimoto, and T. Ohba, “Comparative Study of Side- Wall Roughness Effects on Leakage Current in Through- Silicon Via Interconnects,” IEEE Int’l 3D Sys. Integration Conf. 2011, 2-4 (2012).
[99] Fukozu, K. Kashima, T. Ohba “Application for Rice Plant Cultivation using LSI Integration method.” Proc. The 58th JSAP spring Meeting, 24a-P2-33, (2011)
[100] S. C. Liao, C. H. Lin, P. J. Tzeng, J. C. Chen , S. C. Chen, C. Y. Wu, C. C. Chen, Y. C. Hsin, Y.F. Hsu, S. H. Shen, C. H. Chen, C.C. Wang, D. Y. Hsu, T. C. Hsu, C. H. Ho, Y. S. Kim, H. Kitada, N. Maeda, K. Fujimoto, S. Kodama, T. Ohba, T. K. Ku, and M. J. Kao, “12 Inch Bumpless Wafer-On-Wafer (WOW) Fully Integrated 3DIC Process,” Proc. Advanced Metallization Conf., San Diego, 2011, pp.54-55.
[101] O. Nakatsuka, H. Kitada, Y. S. Kim, Y. Mizushima, T. Nakamura, T. Ohba, and S. Zaima, “Comprehensive Study of Local Strain Structures with High Strain Resolution for Through-Silicon Via Interconnects,” Proc. Advanced Metallization Conf., San Diego, 2011. pp.108-109.
[102] T. Ohba, “Ultra-Thin Silicon Wafer for Three-Dimensional LSI and ECU Applications” ,15th Int’l Conf. on Thin Films, O-S2-04, Nov. 8 (2011).
[103] T. Ohba, “Bumpless Multi Through-Silicon- Via Technology for 3DI using Damascene Process,” 20th ECS Meeting, #1956, The Electrochem. Soc., (2011).
[104] S. Nishihara, E. Haikata, Y. Furumura, and T. Ohba, “Application of Electro-less Ni plating for TSV Cu ECP seed layer,” Proc. Advanced Metallization Conf. (2011).
[105] H. Kitada, Y. Morikawa, N. Maeda, K. Fujimoto, S. Kodama, Y. Mizushima, T. Nakamura, and T. Ohba, “Surface microroughness-induced leakage current in through-silicon via interconnects,” Proc. Advanced Metallization Conf. (2011).
[106] T. Ohba, “Three-Dimensional Integration using Bumpless Through-Silicon-Via and Wafer-on-Wafer Technologies,” Proc. 75th Symp. on Semiconductors and Integrated Circuits Technology, pp. 23-26 (2011).
[107] Y. S. Kim, H. Kitada, R. Ohigashi, M. Ichiyanagi, J. Nakatsuka, I. Kinefuchi, Y. Matsumoto, and T. Ohba, “Hot Spot Cooling Evaluation using Closed-Channel Cooling System (C3S) for MPU 3DI Application,” IEEE Symp. on VLSI Technol., pp. 144-145 (2011).
[108] T. Ohba, “Through-Silicon-Via Technology for Stacked Thin Si Device Wafers,” Proc. on IEEE IWJT, pp. 61-66 (2011).
[109] H. Kitada, N. Maeda, K. Fujimoto, Y. Mizushima, Y. Nakata, T. Nakamura and T. Ohba, “Development of Low Temperature Bump-less TSV Process in 3D Stacking Technology,” IEICE, (2011).
[110] T. Ohba, “Large-Scale 3D Integration Without Extreme Scaling -Can you cut an atom in half?,” Pioneer, ITRI, Nov., pp. 51-57 (2010).
[111] T. Ohba, N. Maeda, H. Kitada, K. Fujimoto, A. Kawai, K. Arai, K. Suzuki, and T. Nakamura, “3D Large Scale Integration Technology using Wafer-on-Wafer (WOW) Stacking,” IEICE Trans. and Electronics, Electronics Soc., J93-C (11), pp. 464-476 (2010).
[112] K. Fujimoto, N. Maeda, H. Kitada, Y. S. Kim, A. Kawai, K. Arai, T. Nakamura, K. Suzuki and T. Ohba, “Development of Multi-Stack Process on Wafer-on-Wafer (WOW),” IEEE CPMT Symp. Jpn. 2010, pp. 157-160 (2010).
[113] T. Ohba, “Front-End-Friendly Bumpless Wafer-on-Wafer (WOW) Technology for 3D Integration and Applications,” 32nd DPS 2010, pp. 95-96 (2010).
[114] T. Ohba, “Bumpless WOW Stacking for Large Scale 3D Integration,” IEEE ICSICT 2010, ed. by Ting-Ao Tang and Yu-Long Jiang, pp. 70-73 (2010).
[115] K. Sakamoto, K. Fujimoto, H. Abe, N. Maeda, H. Kitada, K. Suzuki, and T. Ohba, “Investigation of Total Thickness Variation for Wafer Stack varied with Bonding Pressure and Adhesive Polymer Uniformity,” ADMETA 2010.
[116] T. Ohba, “Prediction of Large Scale Integration from 3-Dimesional viewpoint,” The Planarization and CMP Technical Committee, JSPE, Sept. 10, (2010).
[117] N. Maeda, Y.S. Kim, Y. Hikosaka, T. Eshita, H. Kitada, K. Fujimoto, Y. Mizushima, K. Suzuki, T. Nakamura, A. Kawai, K. Arai, and T. Ohba, “Development of Sub 10-μm Ultra-Thinning Technology Using Device Wafers for 3D Manufacturing of Terabit Memory,” IEEE Symp. on VLSI Technol., pp. 105-106 (2010).
[118] T. Ohba, “Bump-less Wafer-to-Wafer Interconnects using WOW 3DI Technology,” 60th Electronic Components and Technology Conf. (ECTC), CPMT Seminar Advanced Bump and Bump-less Interconnection Technologies, (2010).
[119] T. Ohba, “3D Large Scale Integration Technology using Wafer-on-Wafer (WOW) Stacking,” IEEE Proc. of IITC, 12.1 (2010).
[120] H. Kitada, N. Maeda, K. Fujimoto, Y. Mizushima, Y. Nakata, T. Nakamura, W. Lee, Y-S. Kwon, T. Ohba, “Development of Low Temperature Dielectrics down to 150°C for Multiple TSVs Structure with Wafer-on-Wafer (WOW) Technology,” IEEE Proc. of IITC, 9.6 (2010).
[121] Y. S. Kim, N. Maeda, K. Fujimoto, H. Kitada, A. Kawai, K. Arai, K. Suzuki, Y. Mizushima, T. Nakamura, and T. Ohba, “Evaluation of ultra thinned-wafer employed high performance CMOS devices for Wafer-on-Wafer (WOW) 3D Integration,” Int’l Symposium on Technology Evolution for Silicon Nano-Electronics (ISTESNE), pp. 58-59 (2010).
[122] S. Hamada, T. Horiike, M. Ishikawa, H. Machida, A. Ogura, Y. Ohshita and T Ohba, “Chemical Vapor Deposition of Ge2Sb2Te5 Thin Film for Phase Change Memory,” Proc. 2010 Mat. Res. Soc. Spring meeting, H3.31 (2010).
[123] N. Maeda, H. Kitada1, K. Fujimoto, K. Suzuki, T. Nakamura, A. Kawai, K. Arai, and T. Ohba, “Wafer-on-a-Wafer (WOW) stacking with damascene-contact TSV for 3D integration,” Int’l Symp. on VLSI Technol., System and Applications (2010 VLSI-TSA), Apr., pp. 158-159 (2010).
[124] H. Uehara, J. Katayama, K. Fujimoto, N. Maeda, H. Kitada, K. Suzuki, and T. Ohba, “Development of Permanent Bonding Material for 3DI Process,” AMC2009
[125] Y. Hitomi, K. Fujimoto, S. Tominaga, H. Kitada, and T. Ohba, “Dual Damascene TSV for Wafer-on-a-Wafer (WOW) Using Electro Chemical Plating (ECP) and E-CMP,” AMC2009
[126] K. Fujimoto, M. Akazawa, H. Uehara, J. Katayama, N. Maeda, H. Kitada, K. Suzuki, and T. Ohba, “Wafer Level Alignment Accompanied With Wafer Stacking for wafer-on-a-wafer (WOW) Technology using Polymer Adhesive,” AMC2009
[127] H. Machida, S. Hamada, T. Horiike, M. Ishikawa, A. Ogura, Y. Ohshita, and T. Ohba, “GeSbTe-thin film formation by CVD for next generation memory (PCRAM: Phase Change RAM) materials,” AMC2009.
[128] D. Abe, T. Enomoto, S. Tominaga, H. Kitada, and T. Ohba, “Hybrid e-CMP/CMP Process for Cu Dual Damascene TSV Interconnects by Using Non-Contact Electrode e-CMP Pad,” AMC2009.
[129] K. Fujimoto, N. Maeda, H. Kitada, K. Suzuki, and T. Ohba, “TSV (through silicon via) interconnection on wafer-on-a-wafer (WOW) with MEMS technology,” Solid-State Sensors, Actuators and Microsystems Conf., June 2009, pp. 1877 – 1880 (2009).
[130] Y. S. Kim, A. Tsukune, N. Maeda, H. Kitada, A. Kawai, K. Arai, K. Fujimoto, K. Suzuki, Y. Mizushima, T. Nakamura, T. Ohba, T. Futatsugi, and M. Miyajima, “Ultra Thinning 300-mm Wafer down to 7-μm for 3D Wafer Integration on 45-nm Node CMOS using Strained Silicon and Cu/Low-k Interconnects,” IEEE IEDM Tech. Dig. 365 (2009).
[131] H. Kitada, T. Nakamura, N. Maeda, K. Fujimoto, K. Suzuki, S. Kawai, K. Arai, T. Ohba, “Planarization technology in the wafer level 3-dimentional integration,” Proc. The Japan Society for Precision Engineering (2009) 295.
[132] H. Kitada, N. Maeda, K. Fujimoto, K. Suzuki, A. Kawai, K. Arai, T. Suzuki, T. Nakamura, T. Ohba, “Stress Sensitivity Analysis on TSV Structure of Wafer-on-a-Wafer (WOW) by the Finite Element Method (FEM),” IEEE Proc. of IITC (2009) pp. 107-109.
[133] H. Kitada, N. Maeda, K. Fujimoto, K. Suzuki, T. Nakamura, and T. Ohba, “Effects of thinned multi-stacked wafer thickness on stress distribution in the Wafer-on-a-Wafer (WOW) structure,” Proc. 2009 Mat. Res. Soc. Spring meeting, D8.5/F6.5.
[134] K. Suzuki, N. Maeda, H. Kitada, K. Fujimoto, T. Nakamura, and T. Ohba, “TSV (Through Silicon Via) Interconnection on Wafer-on-a-Wafer (WOW) with MEMS technology,” Proc. 15th Symp. on Microjoining and Assembly Technol. in Electronics, Mate2009 sponsored by Microjoining Commission of JWS, (2009) pp. 283-285.
[135] T. Ohba, “A Novel 3-Dimensional Process for Semiconductor and MEMS Applications using <20-mm Thinned Wafer Multistack,” THERMEC (2009).
[136] N. Maeda, H. Kitada1, K. Fujimoto, K. Suzuki, T. Nakamura, and T. Ohba, “Novel and Production-Worthy Wafer-on-a-Wafer (WOW) Technology Using Self-Aligned TSV (SALT) Interconnects,” Proc. Advanced Metallization Conf. 2008, Eds. M. Naik, R. Shaviv, T. Yoda, and K. Ueno, Mat. Res. Soc., 501 (2009).
[137] Y. Kitaoka, S. Yoshimoto, T. Hirahara, S. Hasegawa, T. Ohba, “Nanometer-scale four-point probe resistance measurements of damascene Cu wires in LSI using carbon nanotube tips”, International Symposium on Surface Science and Nanotechnology, ISSS-5, (2008).
[138] Y. Kitaoka, S. Yoshimoto, T. Hirahara, S. Hasegawa, and T. Ohba, “Nanometer-scale Four Point Probe Resistance Measurements of Cu Wires Using Carbon Nanotube Tips”, H Advanced Metallization Conference 2008: 18th Asian Session
[139] T. Tabata, H. Gotou, T. Yagi, and T. Ohba, “Electrical Characteristics of Electrochemical Plated Cu under Giga Pascal Stresses,” Proc. of Advanced Metallization Conference 2007, Eds. A. J. McKerrow, Y. Shacham-Diamand, S. Shingubara, and Y. Shimogaki (Mat. Res. Soc., PA, 2008), 271.
[140] H. Kudo, K. Ishikawa. M. Nakaishi, A. Tsukune, S. Ozaki, Y. Nakata, S. Akiyama, Y. Mizushima, M. Hayashi , Ade A. Akbar, T. Kouno, H. Iwata, Y. Iba, T. Ohba, T. Futatsugi, T. Nakamura, and T. Sugii, “Enhancing Yield and Reliability by Applying Dry Organic Acid Vapor Cleaning to Copper Contact Via-Bottom for 32-nm Nodes and Beyond,” IEEE IITC, 93 (2007).
[141] T. Ohba, “Material Characteristics and Electrical Modeling of Ultra Thin Copper Oxides in ULSI,” Materials Sci. Forum, vols. 561-565, 1225 (2007).
[142] T. Ohba, “Advanced multilevel interconnect technology,” NATO Advanced Research Workshop on 8th Porous Glasses-Special Glasses (PGL), p. 2 (2007).
[143] M. Sugiyama, I. Gunji, K. Ishikawa, M. Nakaishi, K. Yamashita, T. Ohba, "Reaction mechanism of low-temperature damageless cleaning of Cu2O by HCOOH,” Advanced Metallization Conference 2006 (AMC 2006) pp. 111-116 (2007).
[144] K. Yoneda, J. Ye, and T. Ohba, “Acoustic Emission Analysis of Micro Fractures in Cu/Low-k Interconnects,” Progress in AE XIII, Jpn. Soc. NDI, p. 335 (2006).
[145] J. Nakahira, K. Ishikawa, N. Nishikawa, M. Hayashi, A. A. Akbar, Y. Nakata, Y. Mizushima, H. Kudo, T. Kurahashi, Y. Mishima, Y. Takigawa, M. Nakaishi, T. Ohba, K. Watanabe, “Low Temperature Dry Cleaning Technology using Formic Acid in Cu/Low-k Multilevel Interconnects for 45-nm Node and Beyond,” Proc. Advanced Metallization Conference 2005, Mat. Res. Soc., p. 569 (2006).
[146] T. Ohba and K. Yoneda, “Micro Fracture Analysis of Cu/VLK Interconnects using Acoustic Emission Method,” Proc. in Materials for Advanced Metallization (MAM), Mar. 6, p. 207 (2006).
[147] M. Sugiyama, K. Ishikawa, I. Gunji, K. Yamashita, T. Ohba: "Reduction of Copper Surface with Formic Acid for 32-nm-Node ULSI Metallization: Surface Kinetics Study" 209th Meeting of Electrochemical Society (May 7-11, 2006, Denver CO., USA), p. 828 (2006).
[148] T. Ohba, M. Sugiyama, and K. Yamashita, “High Resolution Analysis of Cu Thin Oxide Formed on Cu in 32-nm Node Cu/Low-k Application,” Proc. In 8th International Conf. on Solid-State and integrated Circuit Technol. (ICSICT), IEEE, ed. by Ting-Ao Tang, Guo-Ping Ru, and Yu-Long Jiang, p. 310 (2006).
[149] T. Ohba, “Advanced Multilevel Interconnect Technologies,” The 56th Annual Meeting of International Society of Electrochemistry, p. 619 (2005).
[150] S. Q. Xiao, Y. Sugita, Y. Morisaki, T. Nakamura, K. Irino, and T. Ohba, “Improved Thermal Stability of HfO2 Films by Atomic Layer Modification Process,” Proc. of International Symposium on Dry Process, p. 73 (2003).
[151] T. Ohba, “Advanced Multilevel Interconnect Technologies,” Proc. Symposium on ULSI Process Integration III, Electrochem. Soc., eds by C. L. Claeys, P. Fazan, F. Gonzalez, R. Singh, and J. Murota, vol. 2003-06, p. 184 (2003).
[152] M. Ikeda, J. Nakahira, Y. Iba, H. Kitada, N. Nishikawa, M. Miyajima, S. Fukuyama, N. Shimizu, K. Ikeda, T. Ohba, I. Sugiura, K. Suzuki, Y. Nakata, S. Doi, N. Awaji, and E. Yano, “A highly reliable nano-clustering silica with low dielectric constant (k < 2.3) and high elastic modulus (E = 10 GPa) for the copper damascene process,” IEEE IITC, p. 71 (2003).
[153] J. Nakahira, K. Suzuki, Y. Iba, I. Sugiura, K. Suzuki, Y. Nakata, S. Fukuyama, E. Yano, and T. Ohba, Proc. of Advanced Metallization Conference 2002, Eds. T. Cale, B. Melnick, S. Zaima, and T. Ohta (Mat. Res. Soc., PA, 2003), p. 749.
[154] Y. Takao, S. Nakai, Y.Tagawa, S. Otsuka, Y. Sambonsugi, K. Sugiyama, H. Oota, Y. Iriyama, R. Nanjyo, H. Nagai, K. Naitoh, R. Nakamura, S. Sekino, A. Yamanoue, N. Horiguchi, T. Yamamoto, M. Kojima, S. Satoh, T.Sugii, M. Kase, K. Suzuki, M. Nakaishi, M. Miyajima, T. Ohba, I. Hanyu, and S. Sugatani, IEEE Symp. VLSI Technol., p. 122 (2002).
[155] S. Nakai, Y. Takao, S. Otsuka, K. Sugiyama, H. Ohta, R. Nanjyo, A. Yamanoue, Y. Iriyama, S. Sekino, H. Nagai, K. Naitoh, R. Nakamura, Y. Sambonsugi, Y. Tagawa, N. Horiguchi, T. Yamamoto, M. Kojima, S. Satoh, S. Sugatani, T. Sugii, K. Yanai, M. Kase, K. Suzuki, M. Nakaishi, M. Miyajima, T. Ohba, and I. Hanyu, IEEE Symp. VLSI Technol., p. 66 (2002).
[156] T. Ohba, “Multilevel Interconnect Technologies in SoC and SiP for 100-nm Node and Beyond,” Proc. of IEEE 6th International Conf. on Solid-State Integrated Circuit Technol. (ICSICT), Eds. Bing-Zong Li, Guo-Ping Ru, Xin-Ping Qu, Paul Yu, and H. Iwai, p. 46 (2001).
[157] T. Ohba, Proc. 29th Int. Workshop on Selective and Functional Film Deposition Technol. (IUVSTA) and 2nd Int. Workshop on Development of Thin Films for future ULSI’s and Nano-Scale Process Integration (JSPS), p. 81 (2000).
[158] T. Ohba, “Current Status of 300mm/0.25-0.18m Technologies,” IEEE 1998 5th International Conf. on Solid-State and Integrated Circuit Technologies, ed, by Min Zhang King Ning Tu, Beijing, Oct. 21, pp. 21-24 (1998).
[159] T. Ohba and H. Tsuchikawa, “Selete Process and Technology Requirements for Manufacturing using 300-mm Wafers,” International Conf. on Metallurgical Coatings and Thin Films, American Vacuum Soc., San Diego, April, p. 332 (1997).
[160] K. Mashimo, K. Inoue, T. Hosoda, T. Ohba, and M. Yasuda, “A Study of WF6 Diffusion and Reaction Kinetics for TiN in W-CVD,” Proc. Advanced Metallization and Interconnect Systems for ULSI Applications in 1995, ed. by R. C. Ellwanger and Shi-Qing Wang (Mat. Res. Soc., Pittsburgh, PA, 1996), 491.
[161] T. Ohba, K. Kakamu, S. Ohira, M. Yamada, and Y. Furumura, “Novel Surface Cleaning using Chlorinetrifluoride for Selective W-CVD Plug,” Proc. Advanced Metallization and Interconnect Systems for ULSI Applications in 1995, ed. by R. C. Ellwanger and Shi-Qing Wang (Mat. Res. Soc., Pittsburgh, PA, 1996), 475.
[162] T. Ohba, “Cu-MOCVD in Advanced Multilevel Metallization,” Proc. on MOCVD Workshop, Korea, July, (1995).
[163] T. Ohba, K. Itoh, T. Suzuki, Y. Furumura, and H. Tsuchikawa, Proc. Advanced Metallization for ULSI Applications in 1993, ed. by D. P. Favreau, Y. Shacham-Diamand (Mat. Res. Soc., Pittsburgh, PA, 1994), 143.
[164] T. Hara, T. Ohba, H. Yagi, and H. Tsuchikawa, "Low Resistivity Tungsten Film Using Diborane Reduction," Proc. Advanced Metallization for ULSI Applications in 1993, ed. by David P. Favreau, Yoshi Shachman-Diamond, and Yasuhiro Horiike (Material Research Society, Pittsburgh, PA 1994), pp.353-359.
[165] K. Kakamu, S. Ohira, T. Ohba, H. Yagi, and H. Tsuchikwa, "Selective W-CVD Using In-situ Temperature Monitoring and Uniform Molecular Flux," Proc. Advanced Metallization for ULSI Applications in 1993, ed. by David P. Favreau, Yoshi Shachman-Diamond, and Yasuhiro Horiike (Material Research Society, Pittsburgh, PA 1994), pp. 427-433.
[166] T. Ohba, T. Suzuki, Y. Furumura, and H. Tsuchikawa, Proc. 44th Symp. On Semiconductors and Integrated Circuits Technol. (Electrochem. Soc. Japan), Tokyo, June 17-18, p. 37 (1993).
[167] T. Suzuki, Ohba, Y. Furumura, and H. Tsuchikawa, "LPCVD-TiN using Hydrazine and TiCl4," Proc. Int. IEEE VLSI Multilevel Interconnection Conf., June 8, pp. 418-423 (1993).
[168] N. Misawa, S. Kishii, T. Ohba, Y. Arimoto, Y. Furumura, and H. Tsuchikawa, "High Performance Planarized CVD-Cu Multi-Interconnection," Proc. Int. IEEE VLSI Multilevel Interconnection Conf., June 8, pp. 353-358 (1993).
[169] T. Ohba., Y. Furumura, and H. Tsuchikawa, “Mechanism of Self-limiting Growth and Film Characteristics of W and WSi2 in Si Reduction Reaction of WF6,” Advanced Metallization for ULSI Applications 1992, ed. by T. S. Cale and F. S. Pintchovski (Material Research Society, Pittsburgh, PA, 1993), 177.
[170] T. Suzuki, T. Ohba, Y. Furumura, and H. Tsuchikawa, “A 0.2-mm contact filling by 450C-hydrazine-reduced TiN film with low resistivity,” IEEE IEDM Tech. Dig., p. 979 (1992).
[171] T. Ohba, Y. Furumura, and H. Tsuchikawa, “Dimethylhydrazine Surface Cleaning and Selective Chemical Vapor Deposition of Tungsten,” Advanced Metallization for ULSI Applications, ed. by V. V. S. Rana, R. V. Joshi, and I. Ohdomari (Material Research Society, Pittsburgh, PA, 1992), 211.
[172] T. Ohba, “Multilevel Metallization Trends in Japan,” Advanced Metallization for ULSI Applications, ed. by V. V. S. Rana, R. V. Joshi, and I. Ohdomari (Material Research Society, Pittsburgh, PA, 1992), 25.
[173] T. Suzuki, N. Misawa, T. Hara, T. Ohba, Y. Furumura, “Resistivity, Contact Resistance and Fluorine Contents of Selective CVD Tungsten Films using Silane Reduction,” Tungsten and Other Advanced Metals for VLSI/ULSI Applications V, ed. by S. Simon Wong and Seijiro Furukawa (Material Research Society, Pittsburgh, PA, 1990), 295.
[174] S. Ohira, T. Suzuki, T. Ohba, M. Kawano, S. Inoue, and J. Nakano, "Contact Resistance for Selectively Deposited W to Si using Two Different Heating Configurations," Proc. Tungsten and Other Advanced Metallization for VLSI/ULSI Applications V, ed. by S. Simon Wong and Seijiro Furukawa (Material Research Society, Pittsburgh, PA, 1990), pp. 289-294.
[175] T. Ohba, T. Suzuki, T. Hara, Y. Furumura, and K. Wada, "Deposition and Properties of Blanket-W using Silane Reduction," Proc. Tungsten and Other Advanced Metallization for VLSI/ULSI Applications V, ed. by S. Simon Wong and Seijiro Furukawa (Material Research Society, Pittsburgh, PA, 1990), pp. 273-279.
[176] T. Hara, T. Suzuki, N. Misawa, T. Ohba, and Y. Furumura, "Surface Cleaning for SiH4-reduced Selective Tungsten," Proc. 11th Int. Conf. on Chemical Vapor Deposition 1990 (CVD-XI), ed. by Karl E. Spear and G. W. Cullen (Electrochem. Soc., Pennington, NJ, 1990), pp. 441-447.
[177] T. Ohba, M. Shirasaki, N. Misawa, T. Suzuki, T. Hara, and Y. Furumura, "Selective and Blanket Tungsten Interconnection and Its Suitability for 0.2-Micron ULSI," Proc. 7th Int. IEEE VLSI Multilevel Interconnection Conf., June 12, pp. 226-232 (1990).
[178] T. Ohba, T. Suzuki, T. Hara, Y. Furumura, and K. Wada, "Selective Chemical Vapor Deposition of Tungsten using Silane and Polysilane Reductions," Proc. Tungsten and Other Advanced Metallization for VLSI Applications IV, ed. by R. S. Blewer and C. M. McConica (Material Research Society, Pittsburgh, PA, 1989), pp. 17-25.
[179] T. Ohba, S. Inoue, and M. Maeda, "Selective CVD Tungsten Silicide for VLSI Applications," IEEE IEDM Tech. Dig., Dec. 6-9, Washington D.C., pp. 213-216 (1987).
[180] T. Ohba, Y. Ohyama, S. Inoue, and M. Maeda, "Evaluation on Selective Deposition of CVD W Films by Measurement of Surface Temperature," Proc. Tungsten and Other Advanced Metallization for VLSI Applications II, ed. by E. K. Broadbent (Material Research Society, Pittsburgh, PA, 1987), pp. 59-66.

Conferences (Japan)

[1] 大場、「いまさら聞けない選択タングステン」、第 32 回シンポジウム 「選択製膜の基礎と応用」、化学工学会 反応工学部会 CVD 反応分科会、Nov. 20, 2020.
[2] 大場、「いよいよ訪れる微細化限界から三次元大規模集積技術へ」、第 21 回 半導体・センサ パッケージング技術展、Jan. 15, 2020.
[3] 大場、「ウエハスケールテラバイト次世代三次元集積技術」、第83回半導体・集積回路技術シンポジウム、2019.
[4] 大場、「3次元積層集積デバイスによる半導体集積回路技術の進展と展望」、第79回応用物理学会秋季学術講演会、19p-432-1、2018.
[5] 鹿島、近藤、伊藤、深水、大場、「月面農場に向けた新栽培法式とその自動化の提案」、2018生態工学会年次大会、オーガナイズドセッション 1 「月面農場ワーキンググループ活動報告」、2018.
[6] 伊藤,石原,鹿島,深水,大場,益、「植物のキモチセンシングを目指したアグリエレクトロニクスの研究」、電子情報通信学会エレクトロニクスソサイエティ大会,BCS-1-6、2017.
[7] 鹿島、深水、大場、「植物の生体活動を知るためのセンシング~半導体製造技術とのコラボレーション~」、日本宇宙生物科学会第31回大会、SP-4, 2017.
[8] 大場、「Ultra-Thinning Technologies for 300-mm Wafer Stack of 3D Semiconductor Application」、日本学術振興会プラズマ材料科学 第153 委員会、Aug. 9, 2017.
[9] 大場、「ウエハ積層を用いた次世代三次元大規模集積技術」、第46回 インターネプコン ジャパン専門技術セミナー、2017.
[10] 大場、特別講演 「極限薄化を用いたWOW三次元大規模集積のシナリオ~ダメージレス加工、精密接合、ウェハの超薄片・小型化、TSVめっき等をキーワードとして~」、第33回精密加工プロセス研究会講演会、2017.
[11] 大場、「WOW(Wafer-on-Wafer)による三次元大規模集積技術」、IEEE CPMT Society Japan Chapter、2016.
[12] 大場, "三次元積層プロセスを用いた次世代大規模集積技術," 第80回半導体集積回路シンポジウム, 8月 2016.
[13] 大場、「三次元大規模集積と微細化の終焉」、第136回プラナリゼーションCMPとその応用技術専門委員会、(2014)
[14] 田岡紀之、中塚理、水島賢子、北田秀樹、Young Suk Kim、中村友二、大場隆之、財満鎭明、「Chip-On-Wafer構造における張り合せSiチップ端近傍の歪分布」、第61 回応用物理学会春季学術講演会講演予稿集、18p-E14-1 (2014).
[15] 中村友二, “表面改質技術:現状と今後の展開,” 応用物理 第82 巻 第5号376(2013)
[16] 水島賢子、北田秀樹,中村友二、谷元昭、越川一茂,鈴木伸介、大場隆之、「IR-OBIRCH 法を用いた三次元積層用LSIのTSVリーク電流評価技術」、Symp. Microjoining Assem Technol Electron、pp. 219-224 (2013).
[17] 田岡紀之、中塚理、水島賢子、北田秀樹、Young Suk Kim、中村友二、大場隆之、財満鎭明、「Wafer‐On‐Wafer構造におけるSi貫通ビア近傍の周期的歪分布」、第74回応用物理学会秋季学術講演会講演予稿集、19A-C10-6 (2013).
[18] 大場、「Bumpless 3D Interconnects for the Tera-scale Bandwidth and High Density Devices Equivalent to <10nm Node Scaling」、応用物理学会春季学術講演会講演予稿集、27P-G9-2 (2013).
[19] 大場、藤本、前田、北田、水島、児玉、YS Kim、「バンプレスTSV配線を用いたテラスケール三次元集積技術」、電気学会電子・情報・システム部門大会、MC5-4 (2013).
[20] 深水克郎、鹿島光司、大場隆之、「LSI インテグレーション手法を用いたイネ水耕栽培システム」、第60 回応用物理学会春季学術講演会講演予稿集、30a-PB1-1 (2013).
[21] 古村雄二、西原晋治、清水紀善、村直美、山本隆一郎、大場隆之、「大気雰囲気下でシリコン結晶膜を連続成長させるHeat-Beam装置」、CVD 反応分科会第16回シンポジウム (2012).
[22] 大場、「ポスト微細化を睨んだ三次元高集積技術~バンプレス配線と薄化ウエハ積層を用いた高密度3DI~」、13th IC Packaging Technol. Expo., ICP-8, Jan. 18-20, Tokyo, 29-46 (2012).
[23] 前田展秀、北田秀樹、藤本興治、キムヨンソク、児玉祥一、善見 誠一、赤澤美雪、水島賢子、大場隆之、「バンプレス接続を用いた極薄COW 積層」、第76回半導体・集積回路技術シンポジウム講演論文集、pp. 35-37 (2012).
[24] 前田展秀,Youngsuk Kim,彦坂幸信,恵下隆,北田秀樹,藤本興治,水島賢子,児玉祥一,大場隆之、「デバイスウェハーの極薄研削の影響」、第73回応用物理学会学術講演会、13p-PB7-4 (2012).
[25] 大場、「Three-Dimensional ULSI Technology for the Post Scaling -High Density 3DI using Bumpless Interconnects and Thinned-Wafer Stack-」、第13回 半導体パッケージング技術展専門技術セミナー、(2012).
[26] 深水克郎、鹿島光司、大場隆之、「LSIインテグレーション手法を用いたイネ水耕栽培システム」、第58回応用物理学関係連合講演会講演予稿集、24A-P2-32 (2011).
[27] 大場、「三次元集積化技術の今後の展開」、第58回応用物理学関係連合講演会講演予稿集、25P-BV-4 (2011).
[28] 古村雄二、村直美、西原晋治、清水紀嘉、大場隆之、「超低コスト半導体膜大気圧連続CVD法の開発」、第72回応用物理学会学術講演会講演予稿集、1A-H-1 (2011).
[29] 西原晋治,拝形絵理,古村雄二,大場隆之、「TSV用Cuメッキシード層へのNi無電解メッキの適用評価」、第72回応用物理学会学術講演会講演予稿集、2P-C-6 (2011).
[30] 大場、「バンプレスTSVおよびWOWを用いた三次元集積化技術」、第75回半導体・集積回路技術シンポジウム、Jul. 7 (2011).
[31] 大場、「バンプレスTSVを用いた高集積化技術の現状と動向」、Electronic Journal第279回 Technical Symposium, Jan. 27, pp. 43-61 (2011).
[32] 大場、「ウェーハ積層を用いた三次元集積技術」、第134回シリコンテクノロジー研究集会、応用物理学会、pp. 6-10 (2011).
[33] 北田秀樹、前田展秀、藤本興治、水島賢子、中田義弘、中村友二、大場 隆之、「3次元積層技術における低温バンプレスTSVプロセス」、電子情報通信学会技術研究報告、110巻(408), pp. 49-53 (2011).
[34] 大場、「バンプレスTSV配線を用いた三次元高集積化技術」、SEMIテクノロジーシンポジウム, Dec. 1, (2010).
[35] 大場隆之、「三次元集積化技術の今後の展開」、第57回応用物理学関係連合講演会講演予稿集、25p-BV-4 (2010).
[36] 大場、「WOWを用いた三次元積層技術-エッチングに優しい三次元量産技術の世界-」、第21回プラズマエレクトロニクス講習会、応用物理学会、pp. 97-106 (2010).
[37] 大場、半導体技術ロードマップ委員会専門部会(WG3), Oct. 15 (2010).
[38] 前田展秀、北田秀樹、藤本興治、鈴木浩助、中村友二、川合章仁、荒井一尚、大場隆之、「ダマシンコンタクトTSVによる三次元集積化」、第73回半導体・集積回路技術シンポジウム講演論文集、pp. 53-55 (2009).
[39] 北田秀樹、中村友二、前田展秀、藤本興治、鈴木浩助、川合章仁、荒井一尚、大場隆之、「ウエハーレベル3 次元積層におけるプラナリゼーション技術」、精密工学会大会学術講演会講演論文集、E01 (2009).
[40] 石川真人、小椋厚志、大下祥雄、町田英明、大場隆之、CVD法によるGaSbTe膜の堆積」第56回応用物理学関係連合講演会講演予稿集、p. 889 (2009).
[41] 前田展秀、北田秀樹、藤本興治、鈴木浩助、中村友二、川合章仁、荒井一尚、大場隆之、「ウェハー積層による三次元集積化」、第56回応用物理学関係連合講演会講演予稿集、p. 862 (2009).
[42] 北田秀樹、前田展秀、藤本興治、鈴木浩助、中村友二、大場隆之、「三次元積層構造における薄化基板へのTSV応力分布の影響」、第56回応用物理学関係連合講演会講演予稿集、p. 862 (2009).
[43] T. Ohba, Technical Workshop for Open Innovation-Green ICE, Dec. 1, (2009).
[44] 大場、「三次元高集積化時代の到来」、エレクトロニクス実装学会(配線板製造技術委員会)EPADs研究会、Nov. 25, pp. 1-32 (2009).
[45] 大場、「ポスト微細化におけるウエハ3次元積層技術」、第12回長野実装フォーラム、Oct. 21, pp. 67-102 (2009).
[46] 大場、「ウエハ3次元積層による低コスト高集積化技術」、Workshop on Advanced Metallization Conf. 2009, Oct. 19, 25.
[47] 大場、「微細化の課題と三次元積層時代の到来」、化学工学会エレクトロニクス部会、Aug. 31 (2009).
[48] 大場、「ポスト微細化をにらんだウエハ積層高集積化技術」、日本学術振興会154委員会「電子デバイス3Dインテグレーションの展望」, July 30 (2009).
[49] 大場、「薄化ウエハ基板を用いた三次元積層技術」、第57回東工大精密工学研究所シンポジウム(第1回集積化MEMS技術研究ワークショップ)、July 14, p. 5 (2009).
[50] 大場、「三次元時代のナノ・マイクロ多層配線技術」、電子情報通信学会専門講習会(北海道支部)、June 4、pp. 3-12 (2009).
[51] 大場、「WOWプロジェクトにおけるNano-Micro多層配線技術」、第71回プラナリゼーションCMP委員会(Proc. 71th Meeting of Planarization CMP Committee)、Feb. 23, pp. 78-88 (2009).
[52] 石川健治、工藤寛、中石雅文、筑根敦弘、尾崎史朗、中田義弘、秋山深一、水島賢子、林雅一、アクバル、河野隆宏、岩田浩、射場義久、大場隆之、二木俊郎、中村友二、杉井寿博、「有機酸ドライクリーニングによるコンタクトビア形成による歩留まり・信頼性の向上」、第72回半導体・集積回路技術シンポジウム、Jul. 10 (2008).
[53] 大場、「ULSI 配線における材料評価と界面のモデリング」、大阪大学特別講演会「次世代シリコンプロセスにおける界面現象と高度制御」、May 28, (2008).
[54] 大場、「Cu配線における極薄膜Cu酸化物の解析」、第55回応用物理学関係連合講演会講演予稿集、p. 128 (2008).
[55] 東野剛之,北岡佑介,吉本真也,平原徹,大場隆之,長谷川修司、「金属被覆CNT 探針を用いたダマシン銅ワイヤのナノメーター電気伝導測定」、日本物理学会第64 回年次大会 (2008).
[56] 大場、「デバイスの微細化限界に対応する-三次元積層化時代の到来」、Proc. in 3D Integration Technology: Learn better, Make better, Dec. 4, (2007).
[57] 大場、「半導体における不確定性限界へのチャレンジ」、電子情報通信学会北海道支部講演会、北見工業大学、Nov. 11, (2007).
[58] 大場、「日本の半導体産業のこれからと実装技術」、IMS, Jul. 27, (2007).
[59] 大場、「最先端LSI半導体の現状と課題」、イビデンセミナー、Jul. 5, (2007).
[60] 田畑友啓,後藤弘匡,八木健彦,大場隆之、「GPa高応力場におけるULSI用Cu材料の電気的特性」、第54回応用物理学関係連合講演会、p. 886 (2007).
[61] 大場、「戦略的コンソーシアムのあり方についてー若手エンジニアに寄せてー」、CMPサマーキャンプ, 大阪大学, Aug. 19, (2004).
[62] 大場、「科学知統合化研究-最先端半導体技術と戦略的コンソーシアムのあり方について」、日立国際セミナー、Mar. 4, (2005).
[63] 大場、「最先端半導体技術と戦略的コンソーシアムのあり方について」、山形大学大学院VBL懇話会、Sep. 21, (2004).
[64] 大場、小林、「コンソーシアムの成果をどう活かすか-半導体技術力の強化に向けて-」、JSTフォーラム第21期第1回例会, Jul. 9, (2004).
[65] 大場、「次世代半導体産業開発とコンソーシアムに期待すること」、Seleteフォーラム、May 26, (2004).
[66] T. Ohba and K. Watanabe, “65nm and 45nm Nodes Cu/VLK Integration,” Materials for Advanced Metallization, Mar. 8, (2004).
[67] T. Ohba, “Advanced Cu/NCS (k<2.4) Interconnect Processing and Integration for 65nm Node and Beyond,” 1st International NanoElectronics Materials Conference (NEMatC), Grenoble, March 2-4, 2004
[68] 大場、「65nm世代高信頼性Cu/NCS多層配線技術および実装技術」、ICP JAPAN2004、第5回 半導体パッケージング技術展併設シンポ、Jan. 29, (2004).
[69] 大場、「65nm世代多層配線技術」、第65回Technical Symposium、電子ジャーナル、Nov. 18, 47 (2003).
[70] T. Ohba, “Current Status and Issues of High-k Technology and Its Application,” The 6th International Forum on Semiconductor Technology (IFST 2003), Feb. 13, (2003).
[71] 肖石琴、杉田義博、森崎祐輔、中村誠、鈴木隣太郎、入野清、大場隆之、「繰り返し成膜法で形成したHfSiONx膜の耐熱性および電気特性の向上」、第64回応用物理学会秋季学術講演会(秋季)予稿集、p. 710 (2003).
[72] T. Ohba, “Multilevel Interconnect Technology for 10-level Cu Dual-damascene/VLK Structure for High Speed 40 nm Gate CMOS Logic Devices,” 21th SEMI Technology Symposium (STS), Dec. 2, (2002).
[73] 大場, 「Cu/Low-kインテグレーションの最新技術」、第6回ASET配線技術研究会、Sept. 2, (2002).
[74] 大場、「Low-K層間絶縁膜の行方 -100nm Node以降の本命- Panel Discussion」、第45回Technical Symposium、電子ジャーナル、Nov. 27, (2001).
[75] T. Ohba, “Multilevel Interconnects Technologies for 100-nm Node and Beyond,” SEMI Forum Japan 2001, Osaka, Aug. 30, (2001).
[76] T. Ohba, Proc. Forum 21, The Semiconductor Industry News, Tokyo, Apr. 16 (2001).
[77] 大場隆之、「最先端半導体におけるCu配線と拡散防止膜」、第62回応用物理学会学術講演会シンポジウム、愛知工業大学、Sept. 12, (2001).
[78] T. Ohba, “Current Status and Prediction Cu/VLK Technologies,” Schumacher’s 12th Dielectrics and Metallization Symposium, San Diego, May 20-22, (2001).
[79] T. Ohba, “Current Status and Prediction Cu/VLK Technologies,” FORUM21, The Semiconductor Industry News, Tokyo, Apr. 16, (2001).
[80] 大場、「Material and Process Challenges in 100-nm, Interconnects Module Technology and Beyond」、第8回研究会日本学術振興会 未来開拓研究推進事業 研究プロジェクト「次世代ULSI用薄膜材料の開発とナノスケールプロセスインテグレーション」, Apr. 5, (2001).
[81] T. Ohba and T. Nakamura, “Current Status and Issues for Cu Interconnect Technology,” Proc. of Scientific and Tech. Div. (VI) Symp., Japan Inst. Metals, Tokyo, Jan. 26, p.5 (2001) in Japanese.
[82] 大場、「Cu/Low-kインテグレーション技術を中心とした多層配線技術の現状と将来」、1st ASET Seminar, Oct. 30, (2000).
[83] 大場、「プラズマCVD技術」、第二回フロンティアプロセス’99、応用物理学会プラズマエレクトロニクス分科会、July 30, (1999).
[84] 大場、「0.13mm以降のメタル配線技術の課題」、第22回Technical Symposium、電子ジャーナル、July 21, (1999).
[85] 大場、「0.13mm以降のメタル配線技術の課題」。第22回テクニカルシンポジウム、電子ジャーナル、July 22, 21-25 (1999).
[86] 大場、「ポスト0.25-mmのメタライゼーションプロセスの方向」、リアライズ社最新技術講座資料集-超LSI製造プロセスにおける今後の配線技術を考える-」、化学会館、Jul. 18, (1997).
[87] 大場、土川、小宮、「300mmウエハプロセス」、電子・情報・システム部門大会(Proc. of the Electronics, Information and Systems Conference, IEEJ)、電気学会、pp. 17-20 (1997).
[88] 大場、「0.25/0.18-mm, 300mm化の現状と量産導入への方向性」、Electric Journal 6th Technical Symposium、電子ジャーナル主催、June 6, 91 (1996).
[89] 大場、「0.25mm対応メタライゼーション技術と300mm化」、第5回半導体プロセスシンポジウム、プレスジャーナル主催、Sept. 19, 69 (1996).
[90] T. Ohba, “Multilevel Interconnects and Related Issues for 0.25-mm and Beyond,” Schumacher Symp., San Diego, Mar., (1996).
[91] T. Ohba, “Current Technology of Multilevel Interconnects and Related Issues for 0.35-mm and Beyond,” Proc. SEMI Technol. Symp. 95, 5-3 (1995).
[92] 大場、「コンタクトホール埋め込み技術」、第4回半導体プロセスシンポジウム、プレスジャーナル主催、Sept. 14, 85 (1995).
[93] 稲垣、各務、大場、八木、「選択W/CoSi2によるソース/ドレイン電極形成」、第42回応用物理学関係連合講演会(春季)予稿集, 29a-K-5, 728 (1995).
[94] 大場隆之、飯尾弘毅、東本正之、原樹、渡部潔、八木春良、古村雄二、「B2H6-H2還元系におけるW-CVDの成膜特性および電気的特性」、第42回応用物理学関係連合講演会(春季)予稿集, 29a-K-9, 730 (1995).
[95] 真下、井上、細田、大場、八木、吉田、「W-CVDにおけるWF6とTiNの反応特性(I)」、第42回応用物理学関係連合講演会(春季)予稿集、29a-K-10, 730 (1995).
[96] 坂井、鈴木、大場、八木、「ヒドラジン還元によるTiN成膜(V)」、第42回応用物理学関係連合講演会(春季)予稿集、29p-K-2, 731 (1995).
[97] 鈴木、坂井、大場、八木、「CVD-TiN膜からの塩素の脱ガス特性評価」、第42回応用物理学関係連合講演会(春季)予稿集、29p-K-3, 731 (1995).
[98] 岡本、大場、山田、古村、「Cu-CVDに及ぼす基板TiNの影響」、第56回応用物理学会秋季学術講演会(秋季)予稿集、27a-PB-4, 696 (1995).
[99] 稲垣、各務、大場、山田、「選択W/CoSi2構造による電極形成(II)」、第56回応用物理学会秋季学術講演会(秋季)予稿集、27p-ZQ-9, 675 (1995).
[100] 各務、大平、大場、塩谷、「ClF3処理を用いた選択W-CVD (I)」、第56回応用物理学会秋季学術講演会(秋季)予稿集、27a-PB-13, 699 (1995).
[101] 大場、真下、水谷、飯尾、井上、山田、「W-CVDにおけるWF6とTiNの反応特性(III)」、第56回応用物理学会秋季学術講演会(秋季)予稿集、27a-PB-16, 700 (1995).
[102] 鈴木、坂井、伊藤、大場、八木、土川、「ヒドラジン還元によるTiN成膜(III)」、第41回応用物理学関係連合講演会(春季)予稿集、29p-ZH-4, 681 (1994).
[103] 大場、伊藤、鈴木、八木、土川、「メチルヒドラジンを用いたTiの低温窒化の検討」、第41回応用物理学関係連合講演会(春季)予稿集、29p-ZH-3, 680 (1994).
[104] 大場、淡路、八木、古村、土川、「Si還元反応によるW薄膜成長(V)-GIDによるWの構造解析-」、第41回応用物理学関係連合講演会(春季)予稿集、29p-ZH-9, 682 (1994).
[105] 大平、大場、倉橋、「SiH4還元反応による選択W-CVDの膜比重」、第41回応用物理学関係連合講演会(春季)予稿集、28a-ZE-5, 704 (1994).
[106] 各務、畑石、大平、大場、古村、「『その場』温度観察および均一分子流束を用いた選択W-CVD (I)」、第41回応用物理学関係連合講演会(春季)予稿集、28a-ZE-6, 704 (1994).
[107] 各務、畑石、大平、大場、古村、「『その場』温度観察および均一分子流束を用いた選択W-CVD (II)」、第41回応用物理学関係連合講演会(春季)予稿集、28a-ZE-7, 705 (1994).
[108] 大場、「多層配線およびコンタクト形成技術」、電気学会第25回超微細製造技術調査専門員会、Nov. 12, (1993).
[109] 大場、「ヒドラジン還元CVD-TiNを用いたコンタクト形成」、第33回VLSI Forum, プレスジャーナル、Sept. 13, 13 (1993).
[110] 大場、古村、「Si還元反応によるW薄膜成長(IV) –析出速度-」、第40回応用物理学関係連合講演会(春季)予稿集、31p-ZY-8, 782 (1993).
[111] 原樹, 大場隆之, 古村雄二, 土川春穂:「ジボラン還元によるCVD-Wの成膜特性」, 第40回応用物理学関係連合講演会(春季)予稿集、31p-ZY-9, 783 (1993).
[112] 鈴木、伊藤、大場、古村、土川、「ヒドラジン還元によるTiN第成膜(I)」、第40回応用物理学関係連合講演会(春季)予稿集、31p-ZY-14, 784 (1993).
[113] 鈴木、伊藤、大場、古村、土川、「ヒドラジン還元によるTiN第成膜(II)」、第40回応用物理学関係連合講演会(春季)予稿集、31p-ZY-15, 785 (1993).
[114] 大場、鈴木、古村、土川、「ヒドラジン還元TiN成長とULSI多層配線技術への応用」、半導体・集積回路技術第44回シンポジウム、電気化学協会電子材料員会主催、June 17, 37-41 (1993).
[115] 大場、「ULSI多層配線の現状とCMPの応用」、ULSIプロセスにおけるCMP(化学的機械研磨)、ポリッシング実用化への課題と展望-超精密平坦化技術コストダウンの方向性-」、グローバルネット主催、Mar. 25, (1993).
[116] 大場、古村、「Si還元反応によるW薄膜成長(I) –吸着・温度・WF6濃度-」、第39回応用物理学関係連合講演会(春季)予稿集、28a-ZH-1, p. 602 (1992).
[117] 大場、古村、土川、「ジメチルヒドラジンを用いた低温・ダメージフリーSi前処理」、第39回応用物理学関係連合講演会(春季)予稿集、30p-ZF-10, p. 691 (1992).
[118] 三沢、大場、古村、土川、「タングステン微細配線の電気特性」、第53回応用物理学会秋季学術講演会(秋季)予稿集、17a-ZR-6, p. 642 (1992).
[119] 大場、古村、「Si還元反応によるW薄膜成長(II) –W薄膜物性-」、第53回応用物理学会秋季学術講演会(秋季)予稿集、17a-ZR-8, p. 643 (1992).
[120] 井上、大場、古村、吉田、「Si還元反応によるW薄膜成長(III) –TEM観察-」、第53回応用物理学会秋季学術講演会(秋季)予稿集、17a-ZR-9, p. 643 (1992).
[121] 井上、原、大場、渡部、「Si還元W/p型Poly-Siのコンタクト抵抗」、第53回応用物理学会秋季学術講演会(秋季)予稿集、17a-ZR-6, p. 646 (1992).
[122] 鈴木、大場、古村、土川、「ヒドラジン還元によるTiN成膜」、電子情報通信学会信学技報(Tech. Rep. of IEICE, SDM92-98)、p. 25 (1992).
[123] 井上、渡部、河野、原、大場、小野、「酸化膜/Poly-Si積層Si基板を用いた選択CVD-Wの成膜特性」、第52回応用物理学会秋季学術講演会(秋季)予稿集、12a-D-6, 753 (1991).
[124] T. Hara, T. Ohba, and Y. Furumura, “Tungsten Contacts and Interconnection Technology,” Proc. Semicon/Kansai-Kyoto Technol. Seminar 91, June 19, pp. 113-120 (1991).
[125] 大場、「CVDタングステン技術とそのブレークスルー」、21世紀に向けた半導体技術問題研究委員会第三回定例会、日本工業技術振興協会(JTTAS)、Mar. 15, 25 (1991).
[126] 大場、「銅配線技術」、日本学術振興会極限構造電子物性第151委員会代18回研究会資料、Dec. 17, 53-60 (1990).
[127] 大場、「埋め込み電極技術」、4th SEMI Tech. Equipment Program Micro-processing 90, Dec. 12, (1990).
[128] 大場隆之、三沢信裕、鈴木寿哉、原樹、古村雄二、「W気相成長におけるb相Wの特性」、第37回応用物理学関係連合講演会(春季)予稿集、28a-ZA-1, 553 (1990).
[129] 李、宮垣、森下、高崎、大場、原、鈴木、西川、「二段階W選択成長法により平坦化されたアモルファスSi積層型CCDイメージセンサー」、第37回応用物理学関係連合講演会(春季)予稿集、28a-SB-4, p. 548 (1990).
[130] 三沢、大場、古村、「CVD-Auの成膜特性」、第37回応用物理学関係連合講演会(春季)予稿集、28p-ZA-8, p. 559 (1990).
[131] 原、三沢、鈴木、大場、古村、「シラン還元を用いた選択CVD-Wの表面処理技術」、第51回応用物理学会秋季学術講演会(秋季)予稿集、28a-SZD-12, p. 667 (1990).
[132] 大平、大場、鈴木、三沢、河野、井上、「選択CVD-W埋め込み膜厚による接合リーク特性」、第51回応用物理学会秋季学術講演会(秋季)予稿集、28a-SZD-16, p. 668 (1990).
[133] 大場、三沢、原、鈴木、古村、和田、「シラン還元反応による選択W成長」、Genus Seminar, Apr. p. 13 (1989).
[134] 三沢、大場、古村、「Auの低温プラズマ気相成長」、第37回半導体・集積回路技術、電気化学協会電子材料委員会、Dec, 7, (1989).
[135] 大場隆之、三沢信裕、原樹、鈴木寿哉、古村雄二、和田邦彦、「CVD-WのULSI多層配線への応用」、EDD-89-32、電気学会、Feb. 3, p. 11 (1989).
[136] 大場隆之、原樹、鈴木寿哉、古村雄二、和田邦彦、「選択/非選択成長領域におけるWSixの組成」、第36回応用物理学関係連合講演会(春季)予稿集、3a-ZF-1, p. 718 (1989).
[137] 大場隆之、古村雄二、和田邦彦、「W気相成長における相Wの特性」、第36回応用物理学関係連合講演会(春季)予稿集、3a-ZF-3, p. 719 (1989).
[138] 大平真也、鈴木寿哉、大場隆之、河野通有、井上信市、中野淳、「シラン還元による選択CVD-Wのコンタクト抵抗の成長温度依存性」、第36回応用物理学関係連合講演会(春季)予稿集、3a-ZF-5, p. 718 (1989).
[139] 原樹、鈴木寿哉、大場隆之、古村雄二、和田邦彦、「シラン還元反応を用いた選択CVD-Wの選択性」、第36回応用物理学関係連合講演会(春季)予稿集、3a-ZF-7, p. 720 (1989).
[140] 大場隆之、鈴木寿哉、原樹、大平真也、古村雄二、「選択成長によるW膜のストレス」、第50回応用物理学会秋季学術講演会(秋季)予稿集、27a-D-3, p. 557 (1989).
[141] 三沢信裕、大場隆之、古村雄二、「CVDによるCuの成長」、第50回応用物理学会秋季学術講演会(秋季)予稿集、29p-D-8, p. 633 (1989).
[142] 大場、「LPCVDによるW成膜」、第18回 VLSI Forum, Dec. 15, pp. 47-56 (1989).
[143] T. Ohba, K. Wada, and K. Yanagida, “Selective Chemical Vapor Deposition of Tungsten for ULSI Applications,” SEMI Technology Symposium (STS), Nov. 28, p. 116 (1988).
[144] 大場隆之、鈴木寿哉、井上信一、前田守、和田邦彦、「選択CVD-WおよびWシリサイドの成長挙動」、ECS日本支部第1回シンポジウム「超LSI CVD技術、Mar. 31, p. 60 (1988).
[145] 大場隆之、鈴木寿哉、大平真也、井上信一、和田邦彦、「SCVD-WSixの反応特性」、第35回応用物理学関係連合講演会(春季)予稿集、30a-V-3, p. 665 (1988).
[146] 井上敬之、梅月愛一郎、鈴木寿哉、大場隆之、栗田和行、井上信一、徳永博司、稲吉勝幸、「CVD-WSixのバリヤ性評価(Al-Au間)」、第35回応用物理学関係連合講演会(春季)予稿集、30a-V-4, p. 666 (1988).
[147] 鈴木寿哉、大場隆之、大平真也、井上信一、「選択CVD-WSixの接合リーク特性」、第35回応用物理学関係連合講演会(春季)予稿集、30a-V-5, p. 666 (1988).
[148] 大場隆之、井上信一、「WF6-SinH2n+2系における低温度領域の選択的成長特性」、第35回応用物理学関係連合講演会(春季)予稿集、30a-V-7, p. 667 (1988).
[149] 大場隆之、鈴木寿哉、原樹、和田邦彦、「WF6-SinH2n+2反応系を用いた選択的成長」、SDM88-36, 電子情報通信学会、June 24, p. 35 (1988).
[150] 鈴木寿哉、原樹、大場隆之、和田邦彦、「SiH4還元による選択CVD-W膜の比抵抗」、第49回応用物理学会秋季学術講演会(秋季)予稿集、4p-a-12, p. 504 (1988).
[151] 大場隆之、井上信一、前田守、「金属及びSi上における選択CVD-W」、第34回応用物理学関係連合講演会(春季)予稿集、28p-B-8, p. 482 (1987).
[152] 鈴木寿哉、大場隆之、井上信一、前田守、「選択CVD-WにおけるSi及びH2還元反応」、第48回応用物理学会秋季学術講演会(秋季)予稿集、17p-Q-11, p. 513 (1987).
[153] 井上信一、大場隆之、前田守、「選択CVD-WSixのVLSIへの応用」、SDM87-151, 電子情報通信学会、Dec. 11, p. 43 (1987).
[154] 大場隆之、大山奏、井上信一、前田守、「W成長における初期反応過程」、第47回応用物理学会秋季学術講演会(秋季)予稿集、30p-N-1, p. 509 (1986).
[155] 大場隆之、大山奏、井上信一、前田守、「選択CVD-Wにおける成長過程-表面温度変化による評価-」、第47回応用物理学会秋季学術講演会(秋季)予稿集、30p-N-2, p. 509 (1986).
[156] 大場隆之、井上信一、塩谷喜美、前田守、「CVD-Alにおける基板の影響」、第47回応用物理学会秋季学術講演会(秋季)予稿集、30p-N-4, p. 510 (1986).
[157] 大場隆之、井上信一、塩谷喜美、前田守、「LPCVD-AlにおけるH2効果」、第46回応用物理学会秋季学術講演会(秋季)予稿集、3a-V-4, p. 412 (1985).

Books

[1] 鹿島光司, 伊藤浩之, 深水克郎, 大場隆之, 「月での米作りのための自動化・センシング技術」、 電子情報通信学会誌, Vol.104 No.2, 123 (2021).
[2] 大場、中村、「三次元集積化技術の現状と将来展望」、応用物理学会誌、第75巻(2)、pp.75-81, 2020.
[3] T. Ohba, "Chapter 5: Wafer-Level Three-Dimensional Integration Using Bumpless Interconnects and Ultrathinning," in 3D Integration in VLSI Circuits, eds. K. Sakuma and K. Iniewski, CRC Press, pp. 85-115, 2018.
[4] 大場、「産業の米、半導体-微細化終焉から三次元へのシナリオ-」、The TRC News, Vol. 120, pp. 1-13 (2015).
[5] 中村友二, “LSIの配線技術と表面科学,” 表面科学Vol. 35, No. 5, pp. 236-243, 2014
[6] 「産業の米、半導体 -微細化終焉から三次元へのシナリオ-」、大場、The TRC NEWS, No. 120, pp. 2-12, Oct. 2014.
[7] 大場、電気工学ハンドブック(第7版)社団法人電気学会編2013年、第8編3章
[8] 半導体デバイスシリーズ3「プロセスインテグレーション」、谷口・鳥海・財満・大場・河崎・綱島共著(權田・谷口編集)、丸善、2010年9月30日
[9] “Advanced Nano-Scale ULSI Interconnects - Fundamental and Practice,” eds., Y. Shacham-Diamand, T. Ohba, T. Osaka and M. Datta, Springer (2008).
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